National Institute of Technology, Uttarakhand M.Tech. in Microelectronics and VLSI Design Admission: Fees, Cutoff, Placement, Ranking

Srinagar Pauri Garhwal

Public/Government|Estd. 2009|NAAC Grade A+

M.Tech. in Microelectronics and VLSI Design Highlights

|

2 Years

|

Total Fees: ₹ 3.0 L

Particulars	Details
Total Fees	₹ 3.0 L
Duration	2 Years
Mode Of Course	Full Time
Seat Breakup	19
Type Of University	Public/Government
Website
Course Level	PG

NIT Uttarakhand M.Tech. in Microelectronics and VLSI Design Important Events

Events	Dates
GATE 2025 Scorecard by paying a fee of INR 500 per test paper	1 Jun, 2025 - 31 Dec, 2025 Ongoing
GATE 2026 Exam Dates	7 Feb, 2026 - 15 Feb, 2026
GATE 2026 Result Declaration	10 Mar, 2026

NIT Uttarakhand M.Tech. in Microelectronics and VLSI Design Expired Events

Events	Dates
GATE 2026 Application Form	28 Aug, 2025 - 7 Oct, 2025
CCMT 2025	14 May, 2025 - 5 Aug, 2025
COAP 2025	13 May, 2025 - 11 Jul, 2025
GATE 2025 Scorecard	28 Mar, 2025 - 31 May, 2025
GATE 2025 results	19 Mar, 2025

GATE Cutoff for M.Tech. in Microelectronics and VLSI Design

ST | All India | All

Rounds	2025
Round 1	271

General | All India | All

Rounds	2025
Round 1	452
Round 2	432
Round 3	424
Round Special Round 1	354
Last Round	350

SC | All India | All

Rounds	2025
Round 1	311
Round 2	291
Round Special Round 1	253
Round Special Round 2	251
Last Round	252

OBCNCL | All India | All

Rounds	2025
Round 1	424
Round 2	424
Round 3	370
Round Special Round 1	343
Last Round	330

EWS | All India | All

Rounds	2025
Round 1	424
Round 2	420
Round 3	377
Round Special Round 1	343