NIT Manipur - National Institute of Technology M.Tech. in VLSI Design And Embedded Systems Admission: Fees, Cutoff, Placement, Ranking

Public/Government|Estd. 2010

M.Tech. in VLSI Design And Embedded Systems Highlights

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2 Years

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Total Fees: ₹ 2.6 L

Particulars	Details
Total Fees	₹ 2.6 L
Duration	2 Years
Mode Of Course	Full Time
Seat Breakup	10
Type Of University	Public/Government
Website
Course Level	PG

NIT Manipur M.Tech. in VLSI Design And Embedded Systems Important Events

Events	Dates
GATE 2025 Scorecard by paying a fee of INR 500 per test paper	1 Jun, 2025 - 31 Dec, 2025 Ongoing

NIT Manipur M.Tech. in VLSI Design And Embedded Systems Expired Events

Events	Dates
CCMT 2025	14 May, 2025 - 5 Aug, 2025
COAP 2025	13 May, 2025 - 11 Jul, 2025
GATE 2025 Scorecard	28 Mar, 2025 - 31 May, 2025
GATE 2025 Final Answer Key	19 Mar, 2025
GATE 2025 results	19 Mar, 2025

M.Tech. in VLSI Design And Embedded Systems Placement

Particular	Statistics
Highest Salary	₹ 47.0 L

Top Recruiters

CapGeminiInfosysKEC International Ltd.Kreeti TechnologyL&T Ecc

L&T InfotechNewgenSamsungValue LabsVirtusa

GATE Cutoff for M.Tech. in VLSI Design And Embedded Systems

General | All India | All

Rounds	2025
Round 1	395
Round 2	381

EWS | All India | All

Rounds	2025
Round 1	370

SC | All India | All

Rounds	2025
Round 1	307
Round 2	280
Round 3	264
Round Special Round 1	271

OBCNCL | All India | All

Rounds	2025
Round 1	358
Round 2	342
Round 3	330

ST | All India | All

Rounds	2025
Round 1	315
Round 3	226