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Dhirubhai Ambani Institute of Information and Communication Technology B.Tech. in Electronics and VLSI Design (EVD) Admission: Fees, Cutoff, Placement, Ranking

Gandhinagar
Private University|Estd. 2001|NAAC Grade A+

B.Tech. in Electronics and VLSI Design (EVD) Highlights

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4 Years
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Total Fees: ₹ 12.0 L
ParticularsDetails
Total Fees₹ 12.0 L
Avg Package₹17,10,000
Duration4 Years
Mode Of CourseFull Time
Seat Breakup21
Type Of UniversityPrivate
Website
Course LevelUG

DAIICT Gandhinagar B.Tech. in Electronics and VLSI Design (EVD) Fee Breakdown 2024

Fee ComponentsAmount
Tuition Fees₹ 12.0 L
Hostel Fees₹ 4.8 L
Other Fees₹ 25.0 K
Total Fees₹ 17.1 L

DAIICT Gandhinagar B.Tech. in Electronics and VLSI Design (EVD) Expired Events

EventsDates
JoSAA 2025 Registration & Choice Filling Starts3 Jun, 2025 - 11 Jul, 2025
JEE Main Result 2025 Session 218 Apr, 2025 - 19 Apr, 2025
JEE Main Answer Key 2025 Session 212 Apr, 2025
JEE Mains 2025 Exam Date Session 22 Apr, 2025 - 9 Apr, 2025
JEE Main Session 2 Admit Card 202528 Mar, 2025

B.Tech. in Electronics and VLSI Design (EVD) Placement

ParticularStatistics
Average Salary₹ 17.1 L
Median Salary₹ 17.5 L
Highest Salary₹ 82.0 L

Top Recruiters

AirtelAmazonFlipkartGoogleLinkedin
OraclePractoSapientTCSZS Associates

B.Tech. in Electronics and VLSI Design (EVD) Ranking

Publisher20242022
NIRF201-250101-150

E-Book And Sample Paper

Other B.E. / B.Tech Courses Offered By DAIICT Gandhinagar

B.Tech. in Mathematics and Computing

Seat Offered: 26|Full Time|4 Years
Median Salary
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Total Fees
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Exam Accepted
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B.Tech. in Information and Communication Technology

Seat Offered: 131|Full Time|4 Years
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B.Tech. (Hons.) in Information and Communication Technology with minor in Computational Science

Seat Offered: 47|Full Time|4 Years
Median Salary
₹ 17.5 L
Total Fees
₹ 12.0 L
Exam Accepted
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